1. Field of the Invention
The present invention relates to a semiconductor memory system, and more particularly, to a memory module having a multi-drop bus structure having multiple termination resistors, and to a memory system having the same.
2. Description of the Related Art
A DRAM uses a multi-drop method in which a plurality of chips are simultaneously connected to a single channel to increase data capacity in a data transmission method. According to the channel in the multi-drop method, as shown in FIG. 1, a plurality of chips 120 through 130 are connected to a single signal line 100. A T-shaped connection portion where lines are connected in three directions exists on the signal line 100 connected to the chips 120 through 130. When data is transmitted, a reflected wave is generated because impedance of the signal line 100 varies at the T-shaped connection portion. Since the reflected wave is generated at each of nodes where the chips 120 through 130 are connected, the total amount of the reflected waves increases as the number of chips connected to a single signal line increases. The reflected wave has a great influence on a transmitted signal as a data transmission speed increases so that the transmission speed of data is limited.
FIG. 2 is a view illustrating a configuration of a bus used for a DDR-II memory system. Referring to FIG. 2, in a DDR-II memory system 200, a DRAM controller 210 and dual in-line memory modules (DIMM) 230 and 260 are connected to a single bus line 220. The DDR-II memory system 200, unlike an SSTL bus used for a DDR SDRAM, has termination resistors 211, 212, 241, 242, 271, and 272 which are arranged in the DRAM controller 210 and the DRAMs 240, 250, 270, and 280. These termination resistors 211, 212, 241, 242, 271, and 272 are referred to as on-die termination (hereinafter, referred to as “ODT”). The ODT resistors 211, 212, 241, 242, 271, and 272 reduce influence generated due to loads by parasite capacitance and inductance existing in the DRAM chips 240, 250, 270, and 280 to improve preservation of a signal, compared to the SSTL bus.
For the maximum signal preservation on the bus line 220, the ODT resistors 211, 212, 241, 242, 271, and 272 are controlled as shown in FIG. 3. in FIG. 3, “Write” signifies storing data on the DRAMs 240, 250, 270, and 280 while “Read” signifies reading data from the DRAMs 240, 250, 270, and 280. During a write operation, when data is stored on a DRAM1 240, for example, the ODT resistors 271 and 272 existing on the DIMM2 260 are turned on while the ODT resistors 241 and 242 existing on the DIMM1 230 are turned off. In this case, the reflected wave is continuously generated from the DIMM2 (260) so that influence on the DIMM1 230 is prevented. Meanwhile, when the data is stored in the DRAM3 chip 270, the ODT resistors 241 and 242 of the DIMM1 230 are turned on while the ODT resistors 271 and 272 of the DIMM2 260 are turned off. Thus, the reflected wave is continuously generated from the DIMM1 230 so that influence on the DIMM2 260 is prevented.
During a read operation, the ODT resistors 211 and 212 of the DRAM controller 210 are turned on. When the data is read from the DRAM1 240, the ODT resistors 271 and 272 of the DIMM2 260 are turned on while the ODT resistors 241 and 242 of the DIMM1 230 are turned off. In contrast, when the data is read from the DRAM3 270, the ODT resistors 241 and 242 of the DIMM1 230 are turned on while the ODT resistors 271 and 272 of the DIMM2 260 are turned off.
Although the bus line 220 of the DDRII memory system 200 enables data transmission at an operation speed less than 1 Gb/s, the data transmission at a speed higher than 1 Gb/s is limited because the influence by the reflected wave increases. Even when the ODT resistors 211, 212, 241, 242, 271, and 272 are on, reflection is continuously generated at a lot of the T-shaped connection portions. That is, considering that the data is stored on the DRAM1 240, since the ODT resistors 271 and 272 of the DIMM2 260 are terminated, the reflected wave is not generated from the DIMM2 260. In the DIMM1 230, however, since input nodes of the DRAM chips 240 and 250 are open, the reflected wave is generated. The reflected wave generated from the DIMM1 230 passes through a connector of the DIMM1 230 again. Since the connector is the T-shaped connection portion, the reflected wave is regenerated and works as a signal interference ISI in storing data in the DRAM1 240 so that the signal preservation is deteriorated. Also, the signal among the reflected wave generated from the DIMM1 230 which proceeds toward the DRAM controller 210 regenerates the reflected wave so as to influence the DRAM1 240 as the ISI.
In the operation of storing or reading data with respect to the DRAMs 270 and 280 in the DIMM2 260, the reflected wave by the ODT resistors 271 and 272 which are in an “OFF” state influences the DIMM2 260 as the ISI. Also, In the DIMM1 230 in which the ODT resistors are in an “ON” state, since the ODT resistors 241 and 242 of the DRAM1 240 which is one of the two chips are in the “ON” state, the reflected wave is generated from the DRAM2 250 including the ODT resistors which are in the “OFF” state.
Thus, a multi-drop bus having a new structure which can reduce the generation of the reflected wave and increase the operation speed up to 3 Gb/s by improving the bus structure used in the DDR-II memory system is demanded.